1. Field of the Invention
This invention is related to the field of processors and, more particularly, to branch prediction in processors.
2. Description of the Related Art
One of the key factors affecting the performance of processors is the management of branch instructions (or more briefly, “branches”). A variety of branch predictors can be used to predict the direction (taken or not taken), the target address, etc. for branches, to allow the processor to fetch ahead of the branches. If the predictions are correct, the next instructions to be executed after each branch may already be preloaded into the processor's pipeline, which may enhance performance over fetching the instructions after executing each branch. Similarly, the next instructions can be speculatively executed and thus can be ready to retire/commit results when the branch is resolved (if the prediction is correct), further enhancing performance.
Branch predictors can be accessed in different fashions, depending on how early in the pipeline the branch predictors are accessed. Generally, the earlier in the pipeline that the predictor is accessed, the less information about the branch is available. For example, if the branch predictor is accessed in parallel with cache access for a fetch, the branch predictor can produce a prediction based on the fetch address. However, the location of the branch instruction is unknown and thus the branch must be located after fetch and the prediction associated with the branch. If the prediction is not taken, there may be another branch in the instructions fetched which could have been predicted but was not predicted.